1. Field of the Invention
The present invention relates to a driving power-supply circuit generating driving voltage for a liquid-crystal display equipment, etc.
2. Description of the Related Art
FIG. 2 is a configuration diagram of a conventional reference voltage generation circuit described in the following patent document 1. (Patent document 1: Japanese Patent Application No. H7-113862.)
The reference voltage generation circuit thereof consists of a reference voltage generating unit, comparing unit, and a driver unit. The reference unit generates a reference voltage VR1, VR2 (wherein VR1>VR2) by a voltage dividing resistor R1, R2, and R3 being connected in serial between the supply voltage VCC and the ground voltage GND. The comparing unit includes a comparator CP1, CP2 comparing the reference voltage VR1, VR2 to an output voltage VO respectively, and a control signal S1, S2 outputs from the CP1, CP2 respectively. The driver unit consists of a P-channel MOS transistor (hereinafter refer to as “PMOS”) and a N-channel MOS transistor (hereinafter refer to as “NMOS”). The PMOS thereof is connected between the supply voltage VCC and an output terminal outputting the output voltage VO and is controlled to on-state or off-state by the control signal S1. The NMOS thereof is connected between the above output terminal and the ground voltage GND and is controlled to on-state or off-state by the control signal S2.
In the above reference voltage generation circuit, both of the control signal S1, S2 become high logic level (hereinafter refer to as level “H”) in the case where VO is higher than VR1. Subsequently, the PMOS become off-sate and the NMOS becomes on-state, then the output terminal is connected to the ground GND through NMOS and the output voltage VO falls.
In the case where VO is lower than VR2, both of the control signal S1, S2 become low logic level (hereinafter refer to as level “L”). Subsequently, the PMOS become on-sate and the NMOS becomes off-state, then the output terminal is connected to the supply voltage VCC through PMOS and the output voltage VO rises.
Further, in the case where VR2 is lower than VO and VO is lower than VR1, the control signal S1, S2 become level “H”, level “L” respectively. Subsequently, both of PMOS and NMOS become off-state, and the output voltage VO is held at a level of between the reference voltage V2 and the reference voltage VR1.
In the above patent document 1, there is no description of the specific circuit configuration regarding the comparator CP1, CP2 of the reference voltage generation circuit, however, it can be assumed that a common operational amplifier is applied thereto.
The operational amplifier consists of a differential amplifier and a constant-current circuit for providing a constant current to the amplifier thereof. For the above reason, a constant current always flows into the comparator CP1, CP2. Since the constant current thereof needs to be increased in proportion to the response speed of the comparator CP1, CP2, there is a problem that the faster the response speed of the reference voltage generation circuit becomes, the more the consumption current of the reference voltage generation circuit becomes, as well as the load current being provided an actual load. The object of the present invention is to decrease the power consumption of the driving power-supply circuit.